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32mx64 bits pc133 sdram so dimm based on 32mx16 sdram with lv ttl, 4 banks & 8k refresh this document is a general product descript ion and is subject to change without notice. hynix semiconductor inc. does not assum e any responsibility for use of circuits described. no pa tent licenses are implied. rev. 0.1/apr. 02 1 hym75v32m636(l)t6 series description the hym75v32m636(l)t6 series are 32mx64bits synchr onous dram modules. the modules are composed of four 32mx16bits cmos synchronous drams in 400mil 54pin ts op-ii package, one 2kbit eeprom in 8pin tssop pack- age on a 144 pin glass-epoxy printed circuit board. tw o 0.33uf and one 0.1uf decoupling capacitors per each sdram are mounted on the pcb. the hym75v32m636(l)t6 series are dual in-line memory modules suitable for easy interchange and addition of 256m bytes memory. the hym75v32m636(l)t6 series are fully synchronous operation re ferenced to the positive edge of the clock . all inputs and outputs are synchronize d with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. features ordering information part no. clock frequency internal bank ref. power sdram package plating hym75v32m636t6-k 133mhz 4 banks 8k normal tsop-ii gold hym75v32m636t6-h 133mhz hym75v32m636lt6-k 133mhz low power HYM75V32M636LT6-H 133mhz ? pc133/pc100mhz support ? 144pin sdram sodimm ? serial presence detect with eeprom ? 1.00? (25.40mm) height pcb with double sided com- ponents ? single 3.3 0.3v power supply ? all device pins are compatible with lvttl interface ? data mask function by dqm ? sdram internal banks : four banks ? module bank : one physical bank ? auto refresh and self refresh ? 8192 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4 or 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks
pc133 sdram so dimm rev. 0.1/apr. 02 2 hym75v32m636(l)t6 series pin description pin pin name description ck0, ck1 clock inputs the system clock input. all other input s are registered to the sdram on the rising edge of clk cke0, cke1 clock enable controls internal cl ock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh /s0 chip select enables or disables all inputs except ck, cke and dqm ba0, ba1 sdram bank address selects bank to be activated during /ras activity selects bank to be read/written during /cas activity a0 ~ a12 address row address : ra0 ~ ra12, column address : ca0 ~ ca9 auto-precharge flag : a10 /ras, /cas, /we row address strobe, column address strobe, write enable /ras, /cas and /we define the operation refer function truth table for details dqm0~dqm7 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq63 data input/output multiplexed data input / output pin vcc power supply (3.3v) power supply for internal circuits and input buffers v ss ground ground scl spd clock input serial presence detect clock input sda spd data input/output serial presence detect data input/output sa0~2 spd address input serial presence detect address input wp write protect for spd write protect for serial presence detect on dimm nc no connection no connection
pc133 sdram so dimm rev. 0.1/apr. 02 3 hym75v32m636(l)t6 series pin assignments note : * ck1 are connected with terminat ion r/c (refer to the block diagram) front side back side front side back side pin no. name pin no. name pin no. name pin no. name 1 vss 2 vss 71 nc 72 nc 3 dq0 4 dq32 73 nc 74 *ck1 5 dq1 6 dq33 75 vss 76 vss 7 dq2 8 dq34 77 nc 78 nc 9 dq3 10 dq35 79 nc 80 nc 11 vcc 12 vcc 81 vcc 82 vcc 13 dq4 14 dq36 83 dq16 84 dq48 15 dq5 16 dq37 85 dq17 86 dq49 17 dq6 18 dq38 87 dq18 88 dq50 19 dq7 20 dq39 89 dq19 90 dq51 21 vss 22 vss 91 vss 92 vss 23 dqm0 24 dqm4 93 dq20 94 dq52 25 dqm1 26 dqm5 95 dq21 96 dq53 27 vcc 28 vcc 97 dq22 98 dq54 29 a0 30 a3 99 dq23 100 dq55 31 a1 32 a4 101 vcc 102 vcc 33 a2 34 a5 103 a6 104 a7 vss 36 vss 105 a8 106 ba0 35 37 dq8 38 dq40 107 vss 108 vss 39 dq9 40 dq41 109 a9 110 ba1 41 dq10 42 dq42 111 a10/ap 112 a11 43 dq11 44 dq43 113 vcc 114 vcc 45 vcc 46 vcc 115 dqm2 116 dqm6 47 dq12 48 dq44 117 dqm3 118 dqm7 49 dq13 50 dq45 119 vss 120 vss 51 dq14 52 dq46 121 dq24 122 dq56 53 dq15 54 dq47 123 dq25 124 dq57 55 vss 56 vss 125 dq26 126 dq58 57 nc 58 nc 127 dq27 128 dq59 59 nc 60 nc 129 vcc 130 vcc voltage key 131 dq28 132 dq60 133 dq29 134 dq61 61 ck0 62 cke0 135 dq30 136 dq62 63 vcc 64 vcc 137 dq31 138 dq63 65 /ras 66 /cas 139 vss 140 vss 67 /we 68 cke1 141 sda 142 scl 69 /s0 70 a12 143 vcc 144 vcc
pc133 sdram so dimm rev. 0.1/apr. 02 4 hym75v32m636(l)t6 series block diagram note : 1. the serial resistor values of dqs are 10ohms 2. the padding capacitance of termination r/c for ck1 is 10pf
pc133 sdram so dimm rev. 0.1/apr. 02 5 hym75v32m636(l)t6 series serial presence detect byte number function description function value note -k -h -k -h byte0 # of bytes written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type sdram 04h byte3 # of row addresses on this assembly 13 0dh 1 byte4 # of column addresses on this assembly 10 0ah byte5 # of module banks on this assembly 1 bank 01h byte6 data width of this assembly 64 bits 40h byte7 data width of this assembly (continued) - 00h byte8 voltage interface standard of this assembly lvttl 01h byte9 sdram cycle time @/ cas latency=3 7.5ns 7.5ns 75h 75h byte10 access time from cloc k @/cas latency= 3 5.4ns 5.4ns 54h 54h byte11 dimm configuration type none 00h byte12 refresh rate/type 7.8125us / self refresh supported 82h byte13 primary sdram width x16 10h byte14 error checking sdram width none 00h byte15 minimum clock delay back to back random column address tccd = 1 clk 01h byte16 burst lenth supported 1,2,4,8,full page 8fh 2 byte17 # of banks on each sdram device 4 banks 04h byte18 sdram device attributes , /cas lataency /cas latency=2,3 06h byte19 sdram device attribut es, /cs lataency /cs latency=0 01h byte20 sdram device attribut es, /we lataency /we latency=0 01h byte21 sdram modul e attributes neither buffered nor registered 00h byte22 sdram device attributes, general +/- 10% voltage tolerence, burst read single bit write, precharge all, auto precharge, early ras precharge 0eh byte23 sdram cycle time @/ cas latency=2 7.5ns 10ns 75h a0h byte24 access time from cl ock @/cas latency=2 5.4ns 6ns 54h 60h byte25 sdram cycle time @/cas latency=1 - 00h byte26 access time from clock @/cas latency=1 - 00h byte27 minimum row precharge time (trp) 15ns 20ns ofh 14h byte28 minimum row active to row active delay (trrd) 15ns 15ns 0fh 0fh byte29 minimum /ras to /cas delay (trcd) 15ns 20ns 0fh 14h byte30 minimum /ras pulse width (tras) 45ns 45ns 2dh 2dh byte31 module bank density 256mb 40h byte32 command and address signal input setup time 1.5ns 1.5ns 15h 15h byte33 command and address signal input hold time 0.8ns 0.8ns 08h 08h byte34 data signal input setup time 1.5ns 1.5ns 15h 15h byte35 data signal input hold time 0.8ns 0.8ns 08h 08h byte36 ~61 superset information (may be used in future) tbd 00h byte62 spd revision intel spd 1.2b 12h 3, 8 byte63 checksum for byte 0~62 - 99h dah byte64 manufacturer jedec id code hynix jeded id adh byte65 ~71 ....manufacturer jedec id code unused ffh byte72 manufacturing location hynix (korea area) hsa (united states area) hse (europe area) hsj (japan area) hss(singapore) asia area 0*h 1*h 2*h 3*h 4*h 5*h 10
pc133 sdram so dimm rev. 0.1/apr. 02 6 hym75v32m636(l)t6 series note : 1. the bank address is excluded 2. 1, 2, 4, 8 for interleave burst type 3. bcd adopted 4. ascii adopted 5. basically hynix writes part no. except for ?hym? in byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 6. not fixed but dependent 7. ck0 connected to dimm, tbd junction temp, cl2(3) su pport, intel defined concurr ent auto precharge support 8. refer to the most recent intel and jedec spd specification 9. these values are applied to pc100 applicat ions only per intel pc sdram specification 10. refer to hynix web site. byte 82~84 for low power part byte numbe r function description function value note -k -h -k -h byte73 manufacturer?s part number (component) 7 (sdram) 37h 4, 5 byte74 manufacturer?s part number (128mb based) 5 35h 4, 5 byte75 manufacturer?s part number (voltage interface) v (3.3v, lvttl) 56h 4, 5 byte76 manufacturer?s part number (memory width) 3 33h 4, 5 byte77 ....manufacturer?s part number (memory width) 2 32h 4, 5 byte78 manufacturer?s part number (module type) m(sodimm) 4dh 4, 5 byte79 manufacturer?s part number (data width) 6 36h 4, 5 byte80 ....manufacturer?s part number (data width) 3 33h 4, 5 byte81 manufacturer?s part number (refresh, sdram bank) 6 (8k refresh, 4banks) 36h 4, 5 byte82 manufacturer?s part number (package type) t 54h 4, 5 byte83 manufacturer?s part number (component configuration) 6 (x16 based) 36h 4, 5 byte84 manufacturer?s part number (hyphen) - (hyphen) 2dh 4, 5 byte85 manufacturer?s part number (min. cycle time) k h 4bh 48h 4, 5 byte86 ~90 manufacturer?s part number blanks 20h 4, 6 byte91 revision code (for component) process code - 4, 6 byte92 ....revision code (for pcb) process code - 3, 6 byte93 manufacturing date year - 3, 6 byte94 ....manufacturing date work week - 6 byte95 ~98 assembly serial number serial number - byte99 ~125 manufacturer specific data (may be used in future) none 00h 7, 8, 9 byte126 reserved 100mhz 64h 7, 8, 9 byte127 intel specification details for 100mhz support refer to note7 8fh 8fh 7, 8, 9 byte128 ~256 unused storage locations - 00h byte number function description function value not e -k -h -k -h byte82 manufacturer?s part number (power) l4ch4, 5 byte83 manufacturer?s part number (package type) t 54h 4, 5 byte84 manufacturer?s part number (component configuration) 6 (x16 based) 36h 4, 5 continued
pc133 sdram so dimm rev. 0.1/apr. 02 7 hym75v32m636(l)t6 series absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. dc operating condition (t a =0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with <=3ns of duration. 3.v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration. ac operating test condition (t a =0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.output load to measure access times is equivalent to two tt l gates and one capacitor (50pf). for details, refer to ac/dc outp ut load circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il -0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement c l 50 pf 1
pc133 sdram so dimm rev. 0.1/apr. 02 8 hym75v32m636(l)t6 series capacitance (ta=25 c , f=1mhz) output load circuit parameter pin symbol -k/h unit min max input capacitance ck0 c i1 20 35 pf cke0 c i2 20 30 pf /s0 c i3 20 30 pf a0~12, ba0, ba1 c i4 20 30 pf /ras, /cas, /we c i5 20 30 pf dqm0~dqm7 ci 6 10 15 pf data input / output capacitance dq0 ~ dq63 c i/o 15 15 pf vtt=1.4v rt=250 ? 50pf output 50pf output dc output load circuit ac output load circuit
pc133 sdram so dimm rev. 0.1/apr. 02 9 hym75v32m636(l)t6 series dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 dc characteristics ii note : 1. i dd1 and i dd4 depend on output loading and cycle rates. specif ied values are measured with the output open 2. min. of trrc (refresh ras cycle ti me) is shown at ac characteristics ii 3.hym75v32m636t6 -k/h 4.hym75v32m636lt6-k/h parameter symbol min. max unit note input leakage current i li -4 4 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol -0.4vi ol = +4ma parameter symbol test condition speed unit note -k -h operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 440 440 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 16 16 ma i dd2ps cke v il (max), t ck = 16 16 precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 160 160 ma i dd2ns cke v ih (min), t ck = input signals are stable. 80 80 active standby current in power down mode i dd3p cke v il (max), t ck = min 56 56 ma i dd3ps cke v il (max), t ck = 56 56 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 320 320 ma i dd3ns cke v ih (min), t ck = input signals are stable. 320 320 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 800 800 ma 1 cl=2 720 720 auto refresh current i dd5 t rrc t rrc (min), all banks active 1760 1760 ma 2 self refresh current i dd6 cke 0.2v 24 24 ma 3 12 12 ma 4
pc133 sdram so dimm rev. 0.1/apr. 02 10 hym75v32m636(l)t6 series ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter 2.access times to be measured with input signal s of 1v/ns edge rate, from 0.8v to 2.0v if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter parameter symbol -k -h unit note min max min max system clock cycle time cas latency = 3 tck3 7.5 1000 7.5 1000 ns cas latency = 2 tck2 7.5 10 ns clock high pulse width tchw 2.5 - 2.5 - ns 1 clock low pulse width tclw 2.5 - 2.5 - ns 1 access time from clock cas latency = 3 tac3 - 5.4 - 5.4 ns 2 cas latency = 2 tac2 - 5.4 - 6 ns data-out hold time toh 2.7 - 2.7 - ns data-input setup time tds 1.5 - 1.5 - ns 1 data-input hold time tdh 0.8 - 0.8 - ns 1 address setup time tas 1.5 - 1.5 - ns 1 address hold time tah 0.8 - 0.8 - ns 1 cke setup time tcks 1.5 - 1.5 - ns 1 cke hold time tckh 0.8 - 0.8 - ns 1 command setup time tcs 1.5 - 1.5 - ns 1 command hold time tch 0.8 - 0.8 - ns 1 clk to data output in low-z time tolz 1 - 1 - ns clk to data output in high-z time cas latency = 3 tohz3 2.7 5.4 2.7 5.4 ns cas latency = 2 tohz2 2.7 5.4 3 6 ns
pc133 sdram so dimm rev. 0.1/apr. 02 11 hym75v32m636(l)t6 series ac characteristics ii note : 1. a new command can be given trrc after self refresh exit parameter symbol -k -h unit note min max min max ras cycle time operation trc 60 - 65 - ns auto refresh trrc 60 - 65 - ns ras to cas delay trcd 15 - 20 - ns ras active time tras 45 100k 45 100k ns ras precharge time trp 15 - 20 - ns ras to ras bank active delay trrd 15 - 15 - ns cas to cas delay tccd 1 - 1 - clk write command to data-in delay twtl 0 - 0 - clk data-in to precharge command tdpl 2 - 2 - clk data-in to active command tdal 5 - 5 - clk dqm to data-out hi-z tdqz 2 - 2 - clk dqm to data-in mask tdqm 0 - 0 - clk mrs to new command tmrd 2 - 2 - clk precharge to data output hi-z cas latency = 3 tproz3 3 - 3 - clk cas latency = 2 tproz2 2 - 2 - clk power down exit time tpde 1 - 1 - clk self refresh exit time tsre 1 - 1 - clk 1 refresh time tref - 64 - 64 ms
pc133 sdram so dimm rev. 0.1/apr. 02 12 hym75v32m636(l)t6 series device operating option table hym75v32m636(l)t6 -k hym75v32m636(l)t6 -h command truth table note : 1. exiting self refresh occurs by asynchronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank addr ess, ra = row address, ca = column address, cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 2clks 2clks 6clks 8clks 2clks 5.4ns 2.7ns 125mhz(8ns) 2clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns command cken-1 cke n cs ras cas we dq m addr a10/ ap ba note mode register set h x l l l l x op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-write h x l l l h x a9 pin high (other pins op code) self refresh 1 entry h l lllhx x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
pc133 sdram so dimm rev. 0.1/apr. 02 13 hym75v32m636(l)t6 series package demension

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